FIG. 18 shows a block diagram of a conventional power control unit shown in FIG. 5, which uses a power control method and a power control program described in the patent document 1. The conventional power control unit is a battery-driven portable one that includes a processor that may be any of a portable telephone, a portable audio device, a portable video camera, a lap-top personal computer, and a PDA (Personal Digital Assistants) device that uses a technique for optimizing its power consumption.
The conventional power control unit as shown in FIG. 18 includes a central processing unit (CPU) (hereinafter, to be referred to as the processor) (21) controlled by software (25) and a power control unit (22). The power control unit (22) is configured by a source voltage/threshold voltage controller, a clock frequency generator, and a timer. The source voltage/threshold voltage controller (hereinafter, to be referred to as the variable DC/DC converter) controls the source voltage or threshold voltage to be applied to the processor (21).
The clock frequency generator (hereinafter, to be referred to as the CPG (Clock Pulse Generator) generates a clock pulse to be supplied to the processor (21) and controls the time width of the clock pulse, that is, a clock frequency. The timer counts the number of pulses at fixed time intervals and supplies the result, that is, time information to the software (25). The timer receives timer clock pulses from the CPG to count the time at fixed time intervals set beforehand by the software (25). The timer clock pulse is different from the clock pulse supplied to the processor (21) from the CPG.
The software (25) is configured by an operating system (hereinafter, to be referred to as the RTOS) (23), a single or plurality of tasks (24), etc. The RTOS (23) retains a single or plurality of executable ready state tasks arranged in order they are to be started or in order of priority. The RTOS (23) can also supply the starting time of the first task to be started to the current active task (24). Each of user programs equivalent to application and middleware programs, etc., as well as the power control program are included in such a single or plurality of tasks (24).
The power control program integrates an execution time between the starting time assigned to the processor (21) with respect to the current active task (24) and the current time to calculate the time to spare in the current active task (24) from the integrated execution time and a preset worst case execution time (hereinafter to be referred to as the WCET) of each target application slice of the subject application program or middleware program. An application slice means each of N slices 1, 2, 3, . . . , N obtained by dividing a task. The WCET of each of the slices 1, 2, 3, . . . , N and the WCET between a given slice and the slice N are obtained through analysis and measurement respectively. If there is any time to spare, the current active task (24) shown in FIG. 18 issues a system call SC to the RTOS (23). The SC is used to set a source voltage and a clock frequency that are both desired. After completing the internal processing in the RTOS (23), the software (25) sends a command C shown in FIG. 2 to the variable DC/DC converter. Receiving the command C, the variable DC/DC converter sets both source voltage and clock frequency that are desired by the software (25) and sends a control signal CS to the processor (21). The processor (21), when receiving the control signal CS, comes to be driven at the source voltage and the clock frequency.
Next, a description will be made for the operation of a task (24) in the RTOS (23). FIG. 19 shows how the state of the task (24) changes in the RTOS. There are four states of the task, that is, the running state (31), the waiting state (32), the ready state (33), and the initial state (34). The initial state (34) means a state in which the subject task (24) is not generated yet. The subject task (24) is generated as follows; at first, an existing task (24a) issues a task generation system call supplied from the RTOS (23) to the system, then the subject task is generated as a task (24c), which then goes into the ready state (33). In the running state (31), the subject task (24) occupies the processor (21) to execute a predetermined processing. In the waiting state (32), the subject task (24d) that has completed the predetermined processing issues an event waiting system call supplied from the RTOS (23) to the system to go out of the running state (31) and enables a different task (24) to occupy the processor (21). The subject task then waits for another event. The task (24d) in the waiting state, when receiving a self-start-up event, goes into the ready state (33).
In the ready state (33), executable tasks (24a) to (24c) are waiting to be allowed to occupy the processor (21) in order of task priority. The task (24a) having the highest task priority among the ready state tasks (24a) to (24c) at that time is dispatched (35) into the running state (31). And, if the task priority of the task (24d) that has moved into the ready state (33) from the waiting state (32) according to the received start-up event is higher than that of the current active task (24a), the current active task (24a) passes the CPU occupation to the task (24d), thereby the task (24a) is pre-emptied (36) into the ready state (33). At the same time, the task (24a) waits to be allowed to go into the running state (31) according to its task priority.
[Patent Document 1] JP-A No. 140787/2003
In prior to the description of this specification, the inventor et al of the present invention have examined the conventional technique of the power control unit described in the patent document 1, particularly with respect to battery-driven information processing systems represented by portable telephones, PDAs, portable digital cameras, portable digital video players, portable digital video cameras, portable digital audio recorders and players, etc.
FIG. 20 is a concept chart of a power control method created by the inventor et al of the present invention so as to use it for the power control unit described in the patent document 1. FIG. 20 is not included in the patent document 1. The vertical axis denotes the processing step of each application slice in an application program and the horizontal axis denotes the processing time of the application program. It is premised here that the number of application slices is K slices. An output time (11) is assumed to be known beforehand. It is also assumed here that the specification of the application program is completed or the processing result of the application program is output in time for the output time (11).
The power control technique described in the patent document 1 controls both source voltage and clock frequency. Consequently, to optimize a power, that is, to minimize the target power consumption, both source voltage and clock frequency must be lowered. And, lowering the clock frequency means executing the processing of the target application program step by step. To realize reduction of such power consumption more effectively, the processing of the target application program must be executed at a low clock frequency up to the last moment of the output time (11). This is why the inventor et al of the present invention have decided to assign the same time interval output time (13) to each application slice according to a linear programming method so that the processing of the application program started at a task starting time (12) will end surely in time for the output time (11). The inventor et al. of the present invention have also assigned a WCET (14) to each application slice beforehand. The WCET (14) is a time interval that is an integer multiple of each sub-output time of which counting begins at the task starting time (12). For example, the WCET (14c) of the k-th application slice set according to the basis of the linear programming method is equivalent to an integrated estimation time obtained by multiplying the sub-output time (13) by k.
At each power control check point (6), a comparison is made between the integrated execution time (15) of the processor (21) counted from the task starting time (12) and the WCET (14) of each application slice (4) to control both of the source voltage and the clock frequency sequentially. For example, assume now that the power control unit can use two combinations of a high source voltage and a high clock frequency, as well as a low source voltage and a low clock frequency to make the above power controlling. If a time difference obtained by subtracting the integrated execution time (15) at the k-th processing ending point (16) of the application slice (4c) counted from the task starting time (12) from the (k−1)-th processing WCET (14d) of the application slice (4d) is greater than the time difference between the (k+1)-th processing WCET (14d) of the application slice (4d) and the k-th processing WCET (14c) of the application slice (4c), that is, a time value obtained by multiplying the sub-output time (13) between the k-th and the (k+1) by a multiple of the high clock frequency, the power consumption is reduced at the k-th processing ending point (16). The output time (11) can be observed strictly, since it is expected that both of the source voltage and the clock frequency that are lowered as described above can be within the WCET (14d) at the (k+1)-th power control check point (6). On the contrary, if the above comparison result becomes smaller, the power must be increased. In other words, both of the source voltage and the clock frequency must be raised. Otherwise, the output time (11) cannot be observed strictly.
As a result of the above examination, it is found that even when the power control unit shown in FIG. 18 is used for the information processing system, two problems related to the optimization of power consumption (energy-saving) are still remained unsolved.
One of the problems causes an event that if an interruption processing is requested to the current active task (24a), the processing of the interrupted task (24a) in the ready state (33) is delayed by the execution time of the high priority task (24d) to be started, so that the time to spare comes to differ from the absolute time up to the output time (11), thereby the power control timing is lost. Hereinafter, such an event will be described with reference to FIG. 21.
FIG. 21 is a graph for describing how the processing of an interrupted task is delayed. For example, if the current active task (24a) is interrupted by a different high priority task (24d) while the k-th application slice (4c) is processed, the interrupted task (24a) is pre-emptied (36), thereby the processing stops. The interrupted task (24a) is dispatched (35) into the running state (31) again when the processing of the task (24b) that has interrupted ends.
However, because the absolute time goes on even while the processing of the interrupted task (24a) stops, the absolute time in the pre-assigned (k+1)-th WCET (14d) comes to be delayed by the execution time (37) of the task (24d) that has interrupted.
Consequently, the (k+1)-th processing ending point (16) comes to include the execution time (37), thereby the power comes to be controlled at the power control check point (6) according to the wrong WCET (14) that is different from the absolute time. The output time (11) also comes to be delayed by the execution time (37). Consequently, the output time saving (11) cannot be assured, thereby the media quality is degraded.
The other problem is an event that if there are many executable tasks (24) that are set in the ready state (33) in the RTOS (23), a jitter occurs in each of those executable tasks (24), thereby both of the processing starting time and the WCET are delayed and no spare time comes to be left, so that the output time cannot be observed. Hereinafter, such an event will be described with reference to FIG. 22.
FIG. 22 shows an illustration for describing how the starting time of a task comes to be delayed just after the task goes into the running state. A task (24a) that is interrupted by another high priority task (24d) and pre-emptied (36) into the ready state and still another task (24c) generated by the task (24a) and set in the ready state (33) are waiting in the ready state (33) respectively so as to occupy the processor (21) as early as possible. However, such low priority tasks (24) as those (24a) and (24c) must wait long in the ready state until they can occupy the processor (21). Usually, the processing of each of such low priority tasks (24a), (24c), etc. is started at the starting time (12) at which the start-up event is received. However, the processing of the task is actually started at a delayed starting time (39) delayed by the ready time (38) and the processing is thus continued just between the delayed starting time (39) and the output time (11). This has been a problem. In addition, the WCET (14) is managed by each application/middleware program. Therefore, if the processing of such an application/middleware program is delayed in starting, the WCET (40) is also delayed by the ready time (38). The final delay WCET (40) thus exceeds the output time (11). This has been another problem. Consequently, the integrated estimation time comes to include an indefinite element, so that the energy-saving effect is lowered.